Until recently, computer systems have primarily utilized single-ended buses and interfaces. Single-ended signaling involves varying voltage with respect to a reference voltage, which is sometimes referred to as “ground,” to signal a logical “1” or “0.” When running multiple signals with respect to the same ground, single-ended signaling provides a cost-effective solution as it only requires one wire per signal.
Despite being less expensive to integrate, there are downsides to single-ended signaling that limit its performance potential. For example, multiple signals sharing the same ground path can lead to crosstalk. Also, differences between ground path and signal path length, coupled with the higher current in the ground path due to signal return-current sharing, can lead to ground potential variations throughout the system. These variations in the reference potential then translate into signaling errors given that the signal potential does not similarly vary with the ground potential. And given that the signal and ground paths do not run in the same proximity to one another, noise injected on the signal path is not similarly injected on the ground path, making single-ended signaling more susceptible to noise. Consequently, in order to maintain a sufficient signal-to-noise ratio, the signal voltages must remain relatively high. High signal voltages require higher transmission power, ultimately limiting transmission distance. And even more importantly, the higher rise and fall times of the higher signal voltages limit interface speed and bandwidth. Given these disadvantages, the computer industry is slowly moving toward differential signaling.
Differential signaling involves the use of two equal-length wires or traces, where each wire carries a mirror of the signal on the other wire. Subtraction of these signals is used to signal a logical “1” or “0.” Since each pair of wires or traces uses its own return path, crosstalk among signals is minimized. Also, equal-length signal paths minimize relative potential differences, providing more consistent readings as path length is varied. Finally, the two wires or traces can be run close to one another, thereby allowing common-mode noise to be cancelled when the signals are subtracted. Given that differential signaling is less susceptible to noise, lower voltages can be used to save transmitting power and allow the use of longer paths or traces. Also, the lower voltages allow higher interface speed and bandwidth given the smaller rise and fall times of the signal.
Having acknowledged the advantages of differential signaling, the computer industry is beginning to shift from single-ended interfaces to differential interfaces. For example, while the latest single-ended PCI interface (e.g., PCI-X 533) offers a theoretical bandwidth of 4.3 GB/s, the sustained bandwidth has shown to be much more modest. Moreover, the speed (e.g., 533 MHz for PCI-X 533) and additional hardware (e.g., almost twice as many pins used in the 64-bit PCI-X interfaces compared to the 32-bit PCI interfaces) used in the PCI-X interface makes it very costly to implement. As such, although PCI and PCI-X were adequate for some time, the need for increased performance at a lower cost has spurred the transition to the latest, full-duplex PCI-Express interface that enables bandwidths up to 8 GB/s in a x16 configuration. And in the future, higher speeds and wider configurations will offer even more bandwidth to accommodate expected computing needs.
Similarly, the computer industry is beginning to realize the need for differential interfaces to display rendered image data. As such, manufacturers are beginning to move from single-ended display interfaces, such as RGB, to differential display interfaces, such as Displayport.
However, the transition to differential signaling will not occur immediately, thereby requiring microprocessor manufacturers to implement backward compatibility with single-ended peripherals. For example, manufacturers of graphics processing units (GPUs) generally agree that differential frame buffer memory offers significant performance improvements over single-ended frame buffer memory, but realize that a market still exists for single-ended I/O interfaces since the transition to differential I/O is in its early stages. Thus, manufacturers desiring to capture both markets are forced to either make a separate GPU solely with a differential I/O interface, or increase the size of the existing single-ended I/O GPU designs to accommodate a differential I/O interface with frame buffer memory. The former alternative is costly as it requires the research, design, and manufacture of a new product. The latter alternative is equally as expensive as it increases both the size and complexity of the integrated circuit devices.
Thus, a need exists for a GPU with a differential interface for coupled devices that maintains backward compatibility with single-ended frame buffer memory without increasing the size, complexity, or cost of the integrated circuit device. The present invention provides a novel solution to these requirements.